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科钛职场速递 - Sky-Five专场(CPU/MCU Design)

发布时间:2019-03-12 访问次数:648次 来源:科钛网 分享:

近期一家初创的芯片设计公司“天之芯”发布招聘信息,如对以下职位感兴趣的朋友请将简历发邮件至 cjiang@wintechm.cn,我们会第一时间推荐适合的职位给您!(企业发布招聘信息全免费)

 

“天之芯”是一家初创的芯片设计公司, 专注于支撑智能物联网和区块链的RISC-V芯片设计,以及产品的商业化和标准化。 天之芯为合作伙伴提供基于RISC-V架构的区块链底层芯片、智能物联网芯片,以及支持RISC-V设计的IP平台,提供免许可、且能快速商用的专用SoC解决方案。 通过桥接软件平台和计算机底层架构,以支撑新兴的互联网应用领域,“天之芯”旨在开拓新兴产业领域,以创新支持世界万物互联的技术。


CPU Design Engineer 中央处理器设计工程师    

工资: 25000 - 50000 月薪

  

The CPU Design Engineer contributes in developing the nextgeneration high-performance RISC-V CPUs tailored to solve new problems in aninnovative way. Sky-Five is looking to develop a state-of-the-art CPU core withoptimum balance among performance, power, area and complexity.

 

Responsibilities:

        Implement the CPU core RTL, verification,and physical design.

        Solidify micro-architecture approaches byconducting CPU micro-architecture trade-offs based on the specification.

        Collaborate with CPU team to assure thedesign meet the performance goals with optimum power, complexity, and areatrade-offs.

        Develop simulation models to allow earlycycle accurate software development.

        Conduct post silicon validation, debugsupport, and power/performance correlation with pre-silicon projections.

 

Qualifications:

        Experience withmicroprocessor logic design demonstrated by having worked on one or more of theRISC-V, ARM, MIPS, SPARC, X86, PowerPC based core-processor designs. Experiencewith low power RISC processor implementation, especially in hardware pipelineprocessing techniques.

        Thorough knowledge ofmicroprocessor architecture including expertise in: instruction fetch anddecode, branch prediction, instruction scheduling and register renaming,out-of-order scheduling and execution, integer and floating point execution.Experience with the load store unit and first level CPU cache, andunderstanding of memory management and cache coherency.

        Fluent in RTL design usingVerilog and experience with simulators and waveform debugging tools.SystemVerilog experience and experience with UVM based environment usage /debugging. High level HDL experience, such as Chisel is a plus.

        Experience in memoryinterface such as DFI is desired. Implementation of bus interface protocol suchas AHB/APB/AXI3/4 experience is desired. Implementation of complex protocols(PCIe or USB or Ethernet, etc.) is desired.

        Exposure to hardwareverification tools and techniques. An interest in formal methods for hardwarespecification and verification a plus.

        MS or PhD in ElectricalEngineering, Computer Science or related fields with 5+ years of CPU designexperience.


 

CPUVerification Engineer     CPU验证工程师

The CPU verification engineer is responsible fordefinition, implementation, debug, and mainte- nance of CPU architectureverification test suites utilizing Assembly and C level code and inter- facinginto a SystemVerilog simulation environment.

 

Responsibilities:

         Develop acomprehensive verification plan and implement verification test cases fromapplications and othersources.

         Workwith architecture, design and software teams tocreate block and subsystem level verification test plans and develop test casesfor verifying next generation RISC proces- sors.

         Create test benches,test plans and test cases starting from the architecture/ implementa- tion specification,and work with architecture, design, verification and software teams to ensuremicro-architecture and design is fully verified/validated across multipleplatforms.

         Debug failures insimulation / emulation of the design on multiple platforms and assist inidentifying / obtaining and verifying designchanges.

         Interface with designengineers and micro-architects to ensure coverage goals are estab- lished andrealized. Help design, develop and use simulation and formal based verifica-tion environments at block, full chip and SoC level to prove the functionalcorrectnessof thedesigns.

 

Qualifications:

         Strong understandingof state of the art of verification techniques, including assertionand metric-driven verification.Experience as a verification architect, establishing the verifi- cationmethodology, tools and infrastructure for high performance IP and/or VLSI de-signs is aplus.

         Direct experience indesign or verification of high performance microprocessors along with broadsoftware design skills establishing coverage goals, writing test plans, and or- ganizing verificationsuites.

         Proficient in designing CPU hardwarespecific tests in assembly language and inC.

         Workingknowledge of CPU systems architecture anddebugging inSystemVerilog basedverificationenvironments.

         Experience withdevelopment of UVM/OVM and/or Verilog,SystemVerilog test benches and usage ofsimulation tools/debug environments such as SynopsysVCS.

         Develop and work withdifferent verification platforms in SystemC/SystemVerilog in- cluding utilization ofEmulation/Prototyping platforms for verifying next generation mul- ti-core SoCdesigns.

         Expertise in Verilog/SystemVerilog, C/C++/SystemC, UVM,Scripting languages like Perl/Python,etc.

         Familiarity withverification management tools and understanding of database manage- ment as itpertains to regressionmanagement.

         PhD or equivalentdegree in Electrical Engineering, Computer Science or related fields with 5years of relevant work experience, or a MS in the same fields with 8 years ofex- perience.

 

Preferences:

         Strong foundation inSoC architecture and verification of next generation RISC proces- sors.

         Experience with gatelevel simulation, power verification, reset verification,contention checking, FPGA programmingandsoftware.

         Familiarity with randomizedverificationtechniques.

         Experience with silicon debug at thetester and boardlevel.

         Experience withformal property checking tools such as Cadence (IEV), Jasper and Syn- opsys(Magellan / VCFormal).

         Experience with mixed-signalverification tools andmethodology.

         Ability to debug failures in RTL and environment on differentverificationplatforms.


 

SoC Design Engineer 数字芯片设计工程师     

工资: 25000 - 50000 月薪

The SoC Design Engineer contributes in developing the nextgeneration high-performance, low-power, RISC-V secureprocessor based SoC.

 

Responsibilities:

        Participate in the development of SoC fromfunctional design/integration, physical implementation through tape-out, andpost silicon validation and testing.

        Analyze SoC definition and specificationincluding power, cost, and performance goals in collaboration with CPUArchitect and other Functional teams.

        Participate in SoC level timingfeasibility studies, cost and power estimation, performance projection,competitive analysis, CPU / Memory /Bus Interface subsystem performanceanalysis and performance tuning.

        Enable and coordinate third party IPintegration.

        Develop, assess and refine RTLdesign through simulation and logic synthesis to achieve power, performance,area and goals.

        Provide guidance to the pre-siliconverification, physical design, post silicon validation, performancecorrelation, and ATE product test.

 

Qualifications:

        Experience in SoCdevelopment. Familiar with modern SoC challenges in terms of power,performance, complexity, and cost tradeoffs.

        Expertise in SoCBus/Fabric/interconnect micro architecture options and their tradeoffs.

        Expertise in SoC levelmemory management and memory coherence logics.

        Expertise in SoC integrationof various subsystems and peripherals, including DRAM, SDC, PCIe, USB,Ethernet, etc.

        Fluent in RTL design usingVerilog and experience with simulators and waveform debugging tools. SystemVerilog experience and experience with UVM based environment usage anddebugging. High level HDL experience such as Chisel is a plus.

        Exposure to formal hardwareverification tools and techniques.

        MS or PhD in ElectricalEngineering, Computer Science or related fields with 5+ years of SoC designexperience.


SoC Design Lead     SoC设计主管

The SoC Design Lead is responsible for developing the nextgeneration high-performance,low-power, RISC-V secure processor basedSoC.

 

Responsibilities:

         Lead all phases of SoC developmentfrom requirement analysis, specification,functionaldesign/integration, physical implementation through tape-out, and post siliconvalidation andtesting.

         Lead the analysis of SoC definitionand specification including power, cost, andperfor- mance goals in collaboration with CPU Architect and otherFunctionalteams.

         Define the overall SoC architecturecollaborating with CPU architect on the SoC Busand MemorySystem.

         Participate in SoC level timingfeasibility studies, cost and power estimation, perfor- mance projection,competitive analysis, CPU / Memory /Bus Interface subsystemper- formance analysis and performancetuning.

         Enable and coordinate third party IPintegration.

         Develop, assess and refine RTL design through simulation and logicsynthesis toachieve power,performance, area andgoals.

         Provide leadership and guidance tothe pre-silicon verification, physical design, post sili- con validation,performance correlation, andATE producttest.

 

Qualifications:

         Experience in SoCdevelopment lead role. Familiar with modern SoC challenges interms of power, performance, complexity,and costtradeoffs.

         Expertise in SoCBus/Fabric/interconnect micro architecture options and theirtradeoffs.

         Expertise in SoC level memory managementand memory coherencelogics.

         Expertise in SoCintegration of various subsystems and peripherals, including DRAM, SDC, PCIe,USB, Ethernet,etc.

         Fluent in RTL design using Verilog and experience with simulators and waveform debug- gingtools. System Verilog experience andexperience with UVM based environment us- ageand debugging. High level HDL experience such as Chisel is aplus.

         Exposure to formal hardwareverification tools andtechniques.

         MS or PhD inElectrical Engineering, Computer Science or related fields with 10+years of SoC designexperience.

         3+ years of experience in a lead roleof SoCdevelopment.


CPU Architect       CPU架构师

The CPU architect isresponsible for creating the next generation processors tailored to solve newproblems in an innovative way. By developing micro-architecture features, theCPU archi- tect will extend the state of the art in CPU by optimizingperformance, area, complexity, and power.

Responsibilities:

              Develop algorithms and craft hardware,extending the state-of-the art for processors, op- timizing along the axes ofperformance, power efficiency, complexity,area, effort, and schedule.

              Implement high-level functional and performancemodels of core, memory subsystem, and I/Osubsystem.

              Use performance models to project performanceof different design options and under- standbottlenecks.

              Analyze benchmark runs and propose experimentsto identify areas for improvement, propose mechanisms to fix them, and presentexperimentresults.

              Develop novel techniques to solve performancebottlenecks, write code to modelsuchnovel ideas, and project expected performancegains.

              Work with designand verification engineers to understand implementation constraints and adaptnew ideas to work within constraints, providing guidance onimplementation andtesting.

              Debug performance and functional issues withhigh-level models, RTL simulation,and silicon.

              Create documentation of architecturalspecifications and customer-facing documentsto describe architecture approaches and performancedata.

 

Qualifications:

              Experience modeling CPU architectures in C/C++required.

              Experience in new architecture techniquedevelopment and associated performancemod-eling and trade-off analysisrequired.

              Knowledge and experience of Verilogand debugging of RTLperformanceissues.

              Experience with branch prediction, hardwareprefetching, and memory subsystemspre-ferred.

              Experience with dynamic code optimizationpreferred.

              PhD or equivalent degree in ElectricalEngineering, Computer Science or relatedfieldswith 8 years of relevant work experience, or a MS in the same fields with 12+years of experience.

              3+ years of experience as a CPUarchitect.


 

CPU Design Lead     CPU设计主管

The CPU Design Lead is responsible for developing the nextgeneration high-performance RISC-V CPUs tailored to solve new problems in aninnovative way. Sky-Five is looking to de- velop a state-of-the-art CPU corewith optimum balance among performance, power, area and complexity.

 

Responsibilities:

         Lead Sky-Five CPU core developmenteffort.

         Create high level CPU corespecification by collaborating with Marketing andCross- functional Engineeringteams.

         Solidify micro-architectureapproaches by conducting CPU micro-architecturetrade-offs based on thespecification.

         Lead the CPU core RTL,verification, and physicalimplementation.

         Collaborate with CPU team to assurethe design meet the performance goals withopti-mum power, complexity, and areatrade-offs.

         Develop simulation models to allow early cycleaccurate softwaredevelopment.

         Conduct post silicon validation,debug support, and power/performance correlationwith pre-siliconprojections.

 

Qualifications:

         Experience withmicroprocessor logic design demonstrated by having worked on one or more of theRISC-V, ARM, MIPS, SPARC, X86, PowerPC based core-processordesigns. Experience with low power RISC processor implementation, especially inhardware pipe- line processingtechniques.

         Thorough knowledge ofmicroprocessor architecture including expertise in: instruction fetch anddecode, branch prediction, instruction scheduling and register renaming,out-of- order scheduling and execution,integer and floating point execution. Experience with the load store unit andfirst level CPU cache, and understanding of memory management and cachecoherency.


         Fluent in RTL design using Verilog and experience with simulators and waveform debug- gingtools. SystemVerilog experience andexperience with UVM based environment us- age/ debugging. High level HDL experience, such as Chisel is aplus.

         Experience in memoryinterface such as DFI is desired. Implementation of bus interface protocol suchas AHB/APB/AXI3/4 experience is desired. Implementation of complex protocols(PCIe or USB or Ethernet, etc.) isdesired.

         Exposure to hardwareverification tools and techniques. An interest in formal methodsfor hardware specification andverification aplus.

         MS or PhD inElectrical Engineering, Computer Science or related fields with 10+years of CPU designexperience.

         3+ years in the lead role of CPU coredevelopment.


如对该职位感兴趣的朋友请将简历发邮件至 cjiang@wintechm.cn,我们会第一时间推荐适合的职位给您!(企业发布招聘信息全免费)